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Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

15.3K Views

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11:42 min

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July 24th, 2015

DOI :

10.3791/52711-v

July 24th, 2015

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1Department of Physics, University of California at Berkeley, 2Department of Chemistry, University of California at Berkeley, 3Department of Chemical and Biomolecular Engineering, University of California at Berkeley, 4National Institute for Materials Science (Japan), 5Materials Sciences Division, Lawrence Berkeley National Laboratory, 6Kavli Energy NanoSciences Institute, University of California at Berkeley and Lawrence Berkeley National Laboratory

This paper details the fabrication process of a gate-tunable graphene device, decorated with Coulomb impurities for scanning tunneling microscopy studies. Mapping the spatially dependent electronic structure of graphene in the presence of charged impurities unveils the unique behavior of its relativistic charge carriers in response to a local Coulomb potential.

Explore More Videos

Graphene
Scanning Tunneling Microscopy
Scanning Tunneling Spectroscopy
Coulomb Impurities
Gate tunable
Electronic Properties
Charge Carriers
Hybrid Device
Fabrication

Chapters in this video

0:05

Title

2:28

Chemical Vapor Deposition of Graphene on a Cu Foil

4:28

Poly(methyl methacrylate) Transfer of Graphene onto Hexagonal Boron Nitride / Silicon Dioxide Chip

6:29

STM Tip Calibration on Au(111) Surface

8:30

Scanning Graphene

9:40

Results: STM Topography Reveals Coulomb Impurities on Graphene

10:44

Conclusion

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